| Issue |
204181
|
| Summary |
[X86][CostModel][AVX512] FP16 cost model prevented vectorization
|
| Labels |
|
| Assignees |
|
| Reporter |
Andarwinux
|
https://godbolt.org/z/3MbdPGPTP
```c
#include <stdint.h>
uint8_t div8(uint8_t a, uint8_t b){
_Float16 r = (_Float16)a / (_Float16)b;
return r;
}
void test(uint8_t * restrict dst,const uint8_t * restrict x, const uint8_t * restrict y)
{
for (uint8_t i = 0; i < 32; i++)
dst[i] = div8(x[i], y[i]);
}
```
-O3 -march=novalake -ffast-math -mrecip=all -fno-unroll-loops -mllvm -force-target-instruction-cost=1
```asm
div8:
vcvtsi2sh xmm0, xmm31, edi
vcvtsi2sh xmm1, xmm31, esi
vrcpsh xmm1, xmm1, xmm1
vmulsh xmm0, xmm1, xmm0
vcvttsh2si eax, xmm0
ret
test:
vpmovzxbw zmm0, ymmword ptr [rsi]
vpmovzxbw zmm1, ymmword ptr [rdx]
vcvtw2ph zmm0, zmm0
vcvtw2ph zmm1, zmm1
vrcpph zmm1, zmm1
vmulph zmm0, zmm1, zmm0
vcvttph2w zmm0, zmm0
vpmovwb ymmword ptr [rdi], zmm0
vzeroupper
ret
```
-O3 -march=diamondrapids -ffast-math -mrecip=all -fno-unroll-loops
```asm
div8:
vcvtsi2sh xmm0, xmm31, edi
vcvtsi2sh xmm1, xmm31, esi
vrcpsh xmm1, xmm1, xmm1
vmulsh xmm0, xmm1, xmm0
vcvttsh2si eax, xmm0
ret
test:
xor eax, eax
.LBB1_1:
vmovd xmm0, dword ptr [rsi + rax]
vmovd xmm1, dword ptr [rdx + rax]
vpmovzxbw xmm0, xmm0
vcvtw2ph xmm0, xmm0
vpmovzxbw xmm1, xmm1
vcvtw2ph xmm1, xmm1
vrcpph xmm1, xmm1
vmulph xmm0, xmm1, xmm0
vcvttph2uw xmm0, xmm0
vpmovwb xmm0, xmm0
vmovd dword ptr [rdi + rax], xmm0
add rax, 4
cmp rax, 32
jne .LBB1_1
ret
```
-O3 -march=diamondrapids -ffast-math -mrecip=all -fno-unroll-loops -mllvm -force-target-instruction-cost=1
```asm
div8:
vcvtsi2sh xmm0, xmm31, edi
vcvtsi2sh xmm1, xmm31, esi
vrcpsh xmm1, xmm1, xmm1
vmulsh xmm0, xmm1, xmm0
vcvttsh2si eax, xmm0
ret
test:
vpmovzxbw ymm0, xmmword ptr [rsi + 16]
vpmovzxbw ymm1, xmmword ptr [rsi]
vpmovzxbw ymm2, xmmword ptr [rdx]
vpmovzxbw ymm3, xmmword ptr [rdx + 16]
vcvtw2ph ymm1, ymm1
vcvtw2ph ymm0, ymm0
vcvtw2ph ymm3, ymm3
vrcpph ymm3, ymm3
vcvtw2ph ymm2, ymm2
vrcpph ymm2, ymm2
vmulph ymm1, ymm2, ymm1
vpsrld xmm2, xmm1, 16
vcvttsh2si eax, xmm2
vcvttsh2si ecx, xmm1
vmulph ymm0, ymm3, ymm0
vmovd xmm2, ecx
vmovshdup xmm3, xmm1
vcvttsh2si ecx, xmm3
vpinsrb xmm2, xmm2, eax, 1
vpsrlq xmm3, xmm1, 48
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, ecx, 2
vshufpd xmm3, xmm1, xmm1, 1
vcvttsh2si ecx, xmm3
vpinsrb xmm2, xmm2, eax, 3
vpsrldq xmm3, xmm1, 10
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, ecx, 4
vshufps xmm3, xmm1, xmm1, 255
vcvttsh2si ecx, xmm3
vpinsrb xmm2, xmm2, eax, 5
vpsrldq xmm3, xmm1, 14
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, ecx, 6
vextractf128 xmm1, ymm1, 1
vcvttsh2si ecx, xmm1
vpinsrb xmm2, xmm2, eax, 7
vpsrld xmm3, xmm1, 16
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, ecx, 8
vmovshdup xmm3, xmm1
vcvttsh2si ecx, xmm3
vpinsrb xmm2, xmm2, eax, 9
vpsrlq xmm3, xmm1, 48
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, ecx, 10
vshufpd xmm3, xmm1, xmm1, 1
vcvttsh2si ecx, xmm3
vpinsrb xmm2, xmm2, eax, 11
vpsrldq xmm3, xmm1, 10
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, ecx, 12
vshufps xmm3, xmm1, xmm1, 255
vcvttsh2si ecx, xmm3
vpinsrb xmm2, xmm2, eax, 13
vpsrldq xmm1, xmm1, 14
vcvttsh2si eax, xmm1
vpinsrb xmm1, xmm2, ecx, 14
vpsrld xmm2, xmm0, 16
vcvttsh2si ecx, xmm2
vpinsrb xmm1, xmm1, eax, 15
vcvttsh2si eax, xmm0
vmovd xmm2, eax
vpinsrb xmm2, xmm2, ecx, 1
vmovshdup xmm3, xmm0
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, eax, 2
vpsrlq xmm3, xmm0, 48
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, eax, 3
vshufpd xmm3, xmm0, xmm0, 1
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, eax, 4
vpsrldq xmm3, xmm0, 10
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, eax, 5
vshufps xmm3, xmm0, xmm0, 255
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, eax, 6
vpsrldq xmm3, xmm0, 14
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, eax, 7
vextractf128 xmm0, ymm0, 1
vcvttsh2si eax, xmm0
vpinsrb xmm2, xmm2, eax, 8
vpsrld xmm3, xmm0, 16
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, eax, 9
vmovshdup xmm3, xmm0
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, eax, 10
vpsrlq xmm3, xmm0, 48
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, eax, 11
vshufpd xmm3, xmm0, xmm0, 1
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, eax, 12
vpsrldq xmm3, xmm0, 10
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, eax, 13
vshufps xmm3, xmm0, xmm0, 255
vcvttsh2si eax, xmm3
vpinsrb xmm2, xmm2, eax, 14
vpsrldq xmm0, xmm0, 14
vcvttsh2si eax, xmm0
vpinsrb xmm0, xmm2, eax, 15
vmovdqu xmmword ptr [rdi + 16], xmm0
vmovdqu xmmword ptr [rdi], xmm1
vzeroupper
ret
```
using force-target-instruction-cost=1 to override the cost worked for NVL (no avx512 entries), but resulted in worse codegen for DMR - the IR is identical.
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