| Issue |
204204
|
| Summary |
AMDGPU needs combine to fold in inf/nan checks into frexp
|
| Labels |
backend:AMDGPU,
floating-point
|
| Assignees |
|
| Reporter |
arsenm
|
The AMDGPU frexp instructions have a defined 0 result for infs and nans. The backend should recognize clamping sequences which produce 0 on edge cases into the instructions.
These cases should all be able to emit a single v_frexp_mant_f32_e32 without a compare or select:
```
define i32 @frexp_nan_clamp_exp(float %x) {
%frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
%frac = extractvalue {float, i32} %frexp, 0
%exp = extractvalue {float, i32} %frexp, 1
%is_nan = fcmp uno float %x, 0.0
%result = select i1 %is_nan, i32 0, i32 %exp
ret i32 %result
}
define i32 @frexp_inf_clamp_exp(float %x) {
%frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
%frac = extractvalue {float, i32} %frexp, 0
%exp = extractvalue {float, i32} %frexp, 1
%abs = call float @llvm.fabs.f32(float %x)
%is_inf = fcmp oeq float %abs, 0x7FF0000000000000
%result = select i1 %is_inf, i32 0, i32 %exp
ret i32 %result
}
define i32 @frexp_inf_or_nan_clamp_exp(float %x) {
%frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
%frac = extractvalue {float, i32} %frexp, 0
%exp = extractvalue {float, i32} %frexp, 1
%abs = call float @llvm.fabs.f32(float %x)
%is_inf = fcmp oeq float %abs, 0x7FF0000000000000
%is_nan = fcmp uno float %x, 0.0
%is_non_finite = or i1 %is_inf, %is_nan
%result = select i1 %is_non_finite, i32 0, i32 %exp
ret i32 %result
}
```
Once this fold is done, we can fix reliance on UB in the OpenCL implementation. OpenCL requires 0 in these cases, but is using the raw llvm intrinsic
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