https://bugs.llvm.org/show_bug.cgi?id=32365
Bug ID: 32365
Summary: [ppc] prefetch instruction blocks the optimization of
st/ld with same address
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: PowerPC
Assignee: unassignedb...@nondot.org
Reporter: car...@google.com
CC: llvm-bugs@lists.llvm.org
Compile the following source code with options -m64 -O2 -mvsx -mcpu=power8
struct C {
struct C *next_;
int length_;
};
int foo(struct C* c){
struct C* next = c->next_->next_;
c->next_ = next;
c->length_--;
__builtin_prefetch(next, 0, 0);
return c->length_;
}
LLVM generates:
foo: # @foo
.Lfunc_begin0:
# BB#0: # %entry
ld 4, 0(3)
lwz 5, 8(3)
ld 4, 0(4)
addi 5, 5, -1
stw 5, 8(3) // store length_
std 4, 0(3)
dcbt 0, 4
ori 2, 2, 0
lwa 3, 8(3) // load length_
blr
The lwa instruction is not necessary since the value of length_ is already in
r5. This problem impacts the performance of tcmalloc.
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