https://bugs.llvm.org/show_bug.cgi?id=37059

            Bug ID: 37059
           Summary: [X86] SLM has incorrect scheduling information for
                    PMULLD
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedb...@nondot.org
          Reporter: craig.top...@gmail.com
                CC: llvm-bugs@lists.llvm.org

I had tried to fix this in r328914, but got perf regressions in some benchmarks
in Intel's internal list. So I reverted it back to old behavior in r329593.

Looking at the benchmarks, they regressed in 32-bit mode and it looks like
register pressure may have increased leading to additional spills. But I
thought 32-bit mode scheduling favored register pressure so I'm not sure what's
going on.

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