https://bugs.llvm.org/show_bug.cgi?id=38001
Bug ID: 38001
Summary: Reading a 8-byte aligned f128 emits a movaps
instruction
Product: tools
Version: 6.0
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: llc
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Created attachment 20496
--> https://bugs.llvm.org/attachment.cgi?id=20496&action=edit
Example LLVM IR
Using load on a f128 with align 8 emits a movaps instruction (on x86-64 with
mmx), which expects a 16-byte aligned address.
An example IR is attached. It can be compiled with
llc -march=x86-64 -mattr=+mmx -O1 movaps.ll
The output of llc -version is:
LLVM (http://llvm.org/):
LLVM version 6.0.0
Optimized build.
Default target: x86_64-pc-linux-gnu
Host CPU: skylake
Registered Targets:
aarch64 - AArch64 (little endian)
aarch64_be - AArch64 (big endian)
amdgcn - AMD GCN GPUs
arm - ARM
arm64 - ARM64 (little endian)
armeb - ARM (big endian)
bpf - BPF (host endian)
bpfeb - BPF (big endian)
bpfel - BPF (little endian)
hexagon - Hexagon
lanai - Lanai
mips - Mips
mips64 - Mips64 [experimental]
mips64el - Mips64el [experimental]
mipsel - Mipsel
msp430 - MSP430 [experimental]
nvptx - NVIDIA PTX 32-bit
nvptx64 - NVIDIA PTX 64-bit
ppc32 - PowerPC 32
ppc64 - PowerPC 64
ppc64le - PowerPC 64 LE
r600 - AMD GPUs HD2XXX-HD6XXX
sparc - Sparc
sparcel - Sparc LE
sparcv9 - Sparc V9
systemz - SystemZ
thumb - Thumb
thumbeb - Thumb (big endian)
x86 - 32-bit X86: Pentium-Pro and above
x86-64 - 64-bit X86: EM64T and AMD64
xcore - XCore
I have installed LLVM from Manjaro repositories.
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