https://bugs.llvm.org/show_bug.cgi?id=38151
Bug ID: 38151
Summary: [X86][SSE] Investigate ISD::MULHU for ISD::SRL
lowering
Product: libraries
Version: trunk
Hardware: PC
OS: Windows NT
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: X86
Assignee: unassignedb...@nondot.org
Reporter: llvm-...@redking.me.uk
CC: andrea.dibia...@gmail.com, craig.top...@gmail.com,
efrie...@codeaurora.org, lebedev...@gmail.com,
llvm-bugs@lists.llvm.org, spatel+l...@rotateright.com
Similar to what we do for rotation lowering, we should be able to use
ISD::MULHU (PMULHUW etc.) to perform vector logical shift right.
We already do something similar for ISD::SHL, except in this case I think we'd
need to treat zero shift elements as a special (pass-through) case.
Constant amounts should be a definite gain (at least for v16i8/v8i16) -
benchmarking would be necessary to determine if non-constant values are worth
it.
Similarly, ISD::SRA might be able to use ISD::MULHS but I haven't investigated
this.
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