https://bugs.llvm.org/show_bug.cgi?id=41281
Bug ID: 41281
Summary: [AMDGPU][MC] Incorrect handling of register syntax
R[X,Y]
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: AMDGPU
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
When parsing registers specified in syntax R[X,Y], assembler does not report an
error if X or Y do not fit in 32 bits. Instead, assembler silently truncates X
and the number of registers (Y-X+1) to 32 bits.
Examples:
// The following code is assembled without errors and result in the same
// code as "v_add_f64 v[0:1], v[0:1], v[1:2]"
v_add_f64 v[0:1], v[0:1], v[0xF00000001:0x2]
v_add_f64 v[0:1], v[0:1], v[0x1:0xF00000002]
In addition, assembler does not check if X or Y are negative. As a result, the
following code breaks assembler:
s_mov_b32 s1, s[0:-1]
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