https://bugs.llvm.org/show_bug.cgi?id=41668
Bug ID: 41668
Summary: unsigned int getFPReg(const llvm::MachineOperand&):
Assertion `Reg >= X86::FP0 && Reg <= X86::FP6 &&
"Expected FP register!"
Product: libraries
Version: trunk
Hardware: PC
OS: Windows NT
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: X86
Assignee: unassignedb...@nondot.org
Reporter: llvm-...@redking.me.uk
CC: craig.top...@gmail.com, llvm-bugs@lists.llvm.org,
llvm-...@redking.me.uk, spatel+l...@rotateright.com
Reduced from https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=14508
source_filename =
"llvm/test/Transforms/LoopVectorize/X86/vectorize-only-for-real.ll"
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.11.0"
define void @accum() #0 {
entry:
%B6 = frem double 4.940660e-324, 0.000000e+00
store double %B6, double* undef
unreachable
}
attributes #0 = { "target-features"="+sse,-avx,-avx2,-sse2" }
llc: /home/simon/LLVM/llvm/lib/Target/X86/X86FloatingPoint.cpp:311: unsigned
int getFPReg(const llvm::MachineOperand&): Assertion `Reg >= X86::FP0 && Reg <=
X86::FP6 && "Expected FP register!"' failed.
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