https://bugs.llvm.org/show_bug.cgi?id=44434
Bug ID: 44434
Summary: check_cfc: dash g generate different code with
SelectionDAGISel
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: enhancement
Priority: P
Component: Common Code Generator Code
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Based on the Bug 44422 - check_cfc: dash g generate different code with
machine-cp. There is another issue that the "isel" pass make different output
in the middle of the optimization, but the issue could not reproduce at the
end, would this be ignored? or is an potential issue.
More analysis about this issue:
[Reproduce]
clang++
$HOME/test-suite/MultiSource/Benchmarks/Bullet/btConvexConvexAlgorithm.cpp -w
-c -mllvm -opt-bisect-limit=669 -O2 -I
$HOME/test-suite/MultiSource/Benchmarks/Bullet/include -o out1.o 2>log1
clang++ -g
$HOME/test-suite/MultiSource/Benchmarks/Bullet/btConvexConvexAlgorithm.cpp -w
-c -mllvm -opt-bisect-limit=699 -O2 -I
$HOME/test-suite/MultiSource/Benchmarks/Bullet/include -o out2.o 2>log2
objdump -d -j .text out1.o > out1.obj
objdump -d -j .text out2.o > out2.obj
colordiff out1.obj out2.obj
[The case related with DAG Instruction Selection]
----------------------------------------------------------
#Before X86 DAG->DAG Instruction Selection:
%60 = load float, float* %12, align 4, !dbg !2196, !tbaa !2011
call void @llvm.dbg.value(metadata float %60, metadata !2144, metadata
!DIExpression()), !dbg !2165
%61 = fsub float %59, %60
# After X86 DAG->DAG Instruction Selection:
%29:fr32 = MOVSSrm_alt %stack.0, 1, $noreg, 0, $noreg, debug-location
DBG_VALUE %29:fr32, $noreg, !"capsuleRadiusB", !DIExpression()
%28:fr32 = SUBSSrr killed %31:fr32(tied-def 0), killed %29:fr32, implicit
$mxcsr
# Expectation:
%28:fr32 = SUBSSrm killed %30:fr32(tied-def 0), %stack.0, 1, $noreg, 0,
$noreg, implicit $mxcsr :: (load 4 from %ir.12, !tbaa !46)
----------------------------------------------------------
In the file lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp,
and the function SelectAllBasicBlock(),
while try to select the instruction with FastISel,
FastIS>tryToFoldLoad() is not implemented because of the dbg_value which
block "fold the load", break by (!isFoldedOrDeadInstruction()).
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