https://bugs.llvm.org/show_bug.cgi?id=44526
Bug ID: 44526
Summary: ComputeKnownBits - minimum guaranteed leading/trailing
zeros in logical right/left shifts
Product: libraries
Version: trunk
Hardware: PC
OS: Windows NT
Status: NEW
Severity: enhancement
Priority: P
Component: Common Code Generator Code
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected], [email protected],
[email protected], [email protected],
[email protected], [email protected]
As detailed in: https://blog.regehr.org/archives/1709
define i32 @foo(i32) {
%a = lshr i32 4, %0
ret i32 %a
}
None of our ComputeKnownBits implementations make use of the fact that logical
left/right shifts will at least retain the trailing/leading zeros of the
shifted value.
I'm currently investigating the SelectionDAG implementation but the InstCombine
+ GlobalISel versions will need handling as well.
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