https://bugs.llvm.org/show_bug.cgi?id=51318
Bug ID: 51318
Summary: [SchedModel] Missing ReadAdvance on the implicit use
of EFLAGS in RM and MR variants of ADC/SBB
Product: libraries
Version: trunk
Hardware: PC
OS: Windows NT
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: X86
Assignee: unassignedb...@nondot.org
Reporter: andrea.dibia...@gmail.com
CC: craig.top...@gmail.com, llvm-bugs@lists.llvm.org,
llvm-...@redking.me.uk, pengfei.w...@intel.com,
spatel+l...@rotateright.com
Example:
```
adc %rax, (%rsp)
```
> llvm-mca -mcpu=btver2 -timeline -iterations=2
The timeline view reports this:
```
Timeline view:
01234
Index 0123456789
[0,0] DeeeeeeER . . adcq %rax, (%rsp)
[1,0] D======eeeeeeER adcq %rax, (%rsp)
```
The load from RSP can start execution before RAX becomes available.
So, most of the load latency can be effectively hidden.
It turns out that we do correctly set a ReadAdvance for the read of RAX.
However, we forgot to do the same for the implicit read EFLAGS.
For reference, this is how it works for normal ADDs (i.e. no carry dependency).
For ADC, the timeline should be identical.
```
Timeline view:
Index 012345678
[0,0] DeeeeeER. addl 4(%rsp), %eax
[0,1] D=eeeeeER addl (%rsp), %eax
```
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