| Issue |
52927
|
| Summary |
[AArch64] LLVM generates integer load + fmov for atomic floating point loads
|
| Labels |
backend:AArch64,
quality-of-implementation,
llvm:codegen
|
| Assignees |
|
| Reporter |
danilaml
|
For this example IR:
```
target triple = "aarch64-none-linux-gnu"
define double @foo(double %d0, double* %p1, double* %p2) {
%d1 = load atomic double, double* %p1 unordered, align 8
%d2 = load atomic double, double* %p2 unordered, align 8
%d3 = fmul double %d1, %d2
%d4 = fadd double %d0, %d3
ret double %d4
}
```
`llc` produces the following assembly:
```foo: // @foo
ldr x8, [x0]
ldr x9, [x1]
fmov d1, x8
fmov d2, x9
fmul d1, d1, d2
fadd d0, d0, d1
ret
```
https://godbolt.org/z/TaxMY9jd3
It looks like the load above is expanded into bitcast + integer load during AtomicExpandPass (there is a TODO there about adding a hook to conditionally do such expansion), and AArch64 is missing td patterns to match the above to `LDRDui` or similar, compared to how it's handled in X86 backend (https://reviews.llvm.org/D60394).
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