| Issue |
54201
|
| Summary |
SIFoldOperands causes Bad machine code: Virtual register killed in block, but needed live out.
|
| Labels |
backend:AMDGPU
|
| Assignees |
|
| Reporter |
jayfoad
|
With the attached [test case](https://github.com/llvm/llvm-project/files/8186866/reduced.txt) I get:
```
$ ~/llvm-debug/bin/llc -march=amdgcn -mcpu=gfx900 -o /dev/null -verify-machineinstrs reduced.txt
# After SI Fold Operands
# Machine code for function _amdgpu_cs_main: IsSSA, TracksLiveness
Function Live Ins: $vgpr0 in %24, $vgpr1 in %25, $vgpr2 in %26, $vgpr3 in %27, $vgpr4 in %28, $vgpr12 in %36, $vgpr13 in %37, $vgpr14 in %38, $vgpr15 in %39, $vgpr16 in %40, $vgpr17 in %41, $vgpr18 in %42, $vgpr19 in %43, $vgpr20 in %44, $vgpr75 in %99, $vgpr76 in %100, $vgpr77 in %101
bb.0..entry:
successors: %bb.12(0x40000000), %bb.1(0x40000000); %bb.12(50.00%), %bb.1(50.00%)
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr75, $vgpr76, $vgpr77
%44:vgpr_32 = COPY $vgpr20
%43:vgpr_32 = COPY $vgpr19
%42:vgpr_32 = COPY $vgpr18
%41:vgpr_32 = COPY $vgpr17
%40:vgpr_32 = COPY $vgpr16
%36:vgpr_32 = COPY $vgpr12
%28:vgpr_32 = COPY $vgpr4
%27:vgpr_32 = COPY $vgpr3
%25:vgpr_32 = COPY $vgpr1
%24:vgpr_32 = COPY $vgpr0
S_CBRANCH_SCC1 %bb.12, implicit undef $scc
S_BRANCH %bb.1
bb.1..lr.ph181.preheader:
; predecessors: %bb.0
successors: %bb.2(0x80000000); %bb.2(100.00%)
%101:vgpr_32 = COPY $vgpr77
%100:vgpr_32 = COPY $vgpr76
%99:vgpr_32 = COPY $vgpr75
%0:vgpr_32 = COPY %24:vgpr_32
%1:vgpr_32 = V_ADD_U32_e64 %28:vgpr_32, %25:vgpr_32, 0, implicit $exec
%3:vgpr_32 = nofpexcept V_RCP_F32_e64 0, %40:vgpr_32, 0, 1, implicit $mode, implicit $exec
%143:sreg_64 = V_CMP_GE_U32_e64 %28:vgpr_32, %27:vgpr_32, implicit $exec
%141:sreg_64 = S_MOV_B64 0
%147:sgpr_32 = S_MOV_B32 0
%152:vgpr_32 = nnan nsz arcp contract afn reassoc nofpexcept V_ADD_F32_e64 0, %42:vgpr_32, 0, %42:vgpr_32, 0, 0, implicit $mode, implicit $exec
%195:sreg_64 = IMPLICIT_DEF
%201:sreg_64 = IMPLICIT_DEF
%208:sreg_64 = IMPLICIT_DEF
bb.2..lr.ph181:
; predecessors: %bb.1, %bb.8
successors: %bb.3(0x40000000), %bb.4(0x40000000); %bb.3(50.00%), %bb.4(50.00%)
%5:sreg_64 = PHI %141:sreg_64, %bb.1, %16:sreg_64, %bb.8
%6:vgpr_32 = PHI %99:vgpr_32, %bb.1, %101:vgpr_32, %bb.8
%144:vgpr_32 = V_MUL_LO_U32_e64 %6:vgpr_32, %1:vgpr_32, implicit $exec
%145:vgpr_32 = V_ADD_U32_e64 killed %144:vgpr_32, %100:vgpr_32, 0, implicit $exec
%180:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %145:vgpr_32, %subreg.sub1
%148:sgpr_256 = REG_SEQUENCE %147:sgpr_32, %subreg.sub0, %147:sgpr_32, %subreg.sub1, %147:sgpr_32, %subreg.sub2, %147:sgpr_32, %subreg.sub3, %147:sgpr_32, %subreg.sub4, %147:sgpr_32, %subreg.sub5, %147:sgpr_32, %subreg.sub6, %147:sgpr_32, %subreg.sub7
%149:vgpr_32 = IMAGE_LOAD_V1_V2 %180:vreg_64, killed %148:sgpr_256, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s96) from custom "ImageResource", align 16)
%153:vgpr_32 = nnan nsz arcp contract afn reassoc V_MAC_F32_e64 0, %149:vgpr_32, 0, %152:vgpr_32, 0, %44:vgpr_32(tied-def 0), 0, 0, implicit $mode, implicit $exec
%154:vgpr_32 = nnan nsz arcp contract afn reassoc nofpexcept V_MUL_F32_e64 0, %40:vgpr_32, 0, killed %153:vgpr_32, 0, 0, implicit $mode, implicit $exec
%155:vgpr_32 = nnan nsz arcp contract afn reassoc V_MAC_F32_e64 0, %36:vgpr_32, 0, killed %154:vgpr_32, 0, %43:vgpr_32(tied-def 0), 0, 0, implicit $mode, implicit $exec
%157:sreg_64 = nofpexcept V_CMP_NGT_F32_e64 0, %155:vgpr_32, 0, 0, 0, implicit $mode, implicit $exec
%158:sreg_64 = nofpexcept V_CMP_GT_F32_e64 0, %155:vgpr_32, 0, 0, 0, implicit $mode, implicit $exec
%8:sreg_64 = SI_IF killed %158:sreg_64, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_BRANCH %bb.3
bb.3 (%ir-block.43):
; predecessors: %bb.2
successors: %bb.5(0x40000000), %bb.6(0x40000000); %bb.5(50.00%), %bb.6(50.00%)
%159:sreg_64 = S_MOV_B64 -1
S_CBRANCH_SCC1 %bb.5, implicit undef $scc
S_BRANCH %bb.6
bb.4.Flow2:
; predecessors: %bb.2, %bb.6
successors: %bb.11(0x40000000), %bb.8(0x40000000); %bb.11(50.00%), %bb.8(50.00%)
%9:sreg_64 = PHI %157:sreg_64, %bb.2, %188:sreg_64, %bb.6
SI_END_CF %8:sreg_64, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
%174:sreg_64 = S_MOV_B64 -1
%10:sreg_64 = SI_IF %9:sreg_64, %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_BRANCH %bb.11
bb.5..lr.ph105:
; predecessors: %bb.3
successors: %bb.7(0x80000000); %bb.7(100.00%)
%160:sreg_64 = S_MOV_B64 0
%182:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
S_BRANCH %bb.7
bb.6.Flow3:
; predecessors: %bb.3, %bb.14
successors: %bb.4(0x80000000); %bb.4(100.00%)
%11:sreg_64 = PHI %159:sreg_64, %bb.3, %22:sreg_64, %bb.14
%189:sreg_64 = S_ANDN2_B64 %157:sreg_64, $exec, implicit-def $scc
%190:sreg_64 = S_AND_B64 %11:sreg_64, $exec, implicit-def $scc
%188:sreg_64 = S_OR_B64 %189:sreg_64, %190:sreg_64, implicit-def $scc
S_BRANCH %bb.4
bb.7 (%ir-block.49):
; predecessors: %bb.5, %bb.13
successors: %bb.10(0x40000000), %bb.13(0x40000000); %bb.10(50.00%), %bb.13(50.00%)
%210:sreg_64 = PHI %208:sreg_64, %bb.5, %22:sreg_64, %bb.13
%205:sreg_64 = PHI %201:sreg_64, %bb.5, %19:sreg_64, %bb.13
%199:sreg_64 = PHI %195:sreg_64, %bb.5, %18:sreg_64, %bb.13
%12:sreg_64 = PHI %160:sreg_64, %bb.5, %21:sreg_64, %bb.13
%13:vgpr_32 = PHI %182:vgpr_32, %bb.5, %27:vgpr_32, %bb.13
%163:vgpr_32 = V_CVT_F32_U32_e64 %13:vgpr_32, 0, 0, implicit $mode, implicit $exec
%165:vgpr_32 = nnan nsz arcp contract afn reassoc nofpexcept V_MUL_F32_e64 0, killed %163:vgpr_32, 0, killed %3:vgpr_32, 0, 0, implicit $mode, implicit $exec
%166:vgpr_32 = nnan nsz arcp contract afn reassoc nofpexcept V_MUL_F32_e64 0, killed %165:vgpr_32, 0, %41:vgpr_32, 0, 0, implicit $mode, implicit $exec
%168:sreg_64 = nofpexcept V_CMP_NLG_F32_e64 0, killed %166:vgpr_32, 0, 0, 0, implicit $mode, implicit $exec
%196:sreg_64 = S_OR_B64 %199:sreg_64, $exec, implicit-def $scc
%202:sreg_64 = S_OR_B64 %205:sreg_64, $exec, implicit-def $scc
%14:sreg_64 = SI_IF killed %168:sreg_64, %bb.13, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_BRANCH %bb.10
bb.8.Flow4:
; predecessors: %bb.4, %bb.11
successors: %bb.9(0x04000000), %bb.2(0x7c000000); %bb.9(3.12%), %bb.2(96.88%)
%15:sreg_64 = PHI %174:sreg_64, %bb.4, %193:sreg_64, %bb.11
SI_END_CF %10:sreg_64, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
%16:sreg_64 = SI_IF_BREAK %15:sreg_64, %5:sreg_64, implicit-def dead $scc
SI_LOOP %16:sreg_64, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_BRANCH %bb.9
bb.9 (%ir-block.60):
; predecessors: %bb.8
SI_END_CF %16:sreg_64, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_ENDPGM 0
bb.10 (%ir-block.61):
; predecessors: %bb.7
successors: %bb.13(0x80000000); %bb.13(100.00%)
%200:sreg_64 = S_ANDN2_B64 %196:sreg_64, $exec, implicit-def $scc
%197:sreg_64 = COPY %200:sreg_64
%206:sreg_64 = S_ANDN2_B64 %202:sreg_64, $exec, implicit-def $scc
%207:sreg_64 = S_AND_B64 %143:sreg_64, $exec, implicit-def $scc
%203:sreg_64 = S_OR_B64 %206:sreg_64, %207:sreg_64, implicit-def $scc
S_BRANCH %bb.13
bb.11.._crit_edge144:
; predecessors: %bb.4
successors: %bb.8(0x80000000); %bb.8(100.00%)
%193:sreg_64 = S_XOR_B64 $exec, -1, implicit-def $scc
S_BRANCH %bb.8
bb.12.._crit_edge182:
; predecessors: %bb.0
S_ENDPGM 0
bb.13.Flow:
; predecessors: %bb.7, %bb.10
successors: %bb.14(0x04000000), %bb.7(0x7c000000); %bb.14(3.12%), %bb.7(96.88%)
%19:sreg_64 = PHI %202:sreg_64, %bb.7, %203:sreg_64, %bb.10
%18:sreg_64 = PHI %196:sreg_64, %bb.7, %197:sreg_64, %bb.10
SI_END_CF %14:sreg_64, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
%171:sreg_64 = S_XOR_B64 %18:sreg_64, -1, implicit-def dead $scc
%21:sreg_64 = SI_IF_BREAK %19:sreg_64, %12:sreg_64, implicit-def dead $scc
%211:sreg_64 = S_ANDN2_B64 %210:sreg_64, $exec, implicit-def $scc
%212:sreg_64 = S_AND_B64 %171:sreg_64, $exec, implicit-def $scc
%22:sreg_64 = S_OR_B64 %211:sreg_64, %212:sreg_64, implicit-def $scc
SI_LOOP %21:sreg_64, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_BRANCH %bb.14
bb.14.loop.exit.guard:
; predecessors: %bb.13
successors: %bb.6(0x80000000); %bb.6(100.00%)
SI_END_CF %21:sreg_64, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_BRANCH %bb.6
# End machine code for function _amdgpu_cs_main.
*** Bad machine code: Virtual register killed in block, but needed live out. ***
- function: _amdgpu_cs_main
- basic block: %bb.7 (0xa891970)
Virtual register %3 is used after the block.
LLVM ERROR: Found 1 machine code errors.
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
```
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