| Issue |
56036
|
| Summary |
[AMDGPU][GFX11] Incorrect src0 type of dpp and dpp8 variants of v_cvt_*_e64
|
| Labels |
bug,
backend:AMDGPU,
mc
|
| Assignees |
dpreobra
|
| Reporter |
dpreobra
|
These instructions should only accept VGPRs as src0, however SGPRs are accepted as well.
An example of failed test:
v_cvt_f32_i32_e64_dpp v5, s1 dpp8:[0,0,0,0,0,0,0,0]
Expected result:
an error
Actual output:
[0x05,0x00,0x85,0xd5,0xe9,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
Moreover, this bug results in incorrect decoding of valid code.
An example of failed test:
0x05,0x00,0x85,0xd5,0xe9,0x00,0x00,0x00,0x01,0x00,0x00,0x00
Expected output:
v_cvt_f32_i32_e64_dpp v5, v1 dpp8:[0,0,0,0,0,0,0,0]
Actual result:
v_cvt_f32_i32_e64_dpp v5, s1 dpp8:[0,0,0,0,0,0,0,0]
A fix is being tested.
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