| Issue | 56080 |
|---|---|
| Summary | AMDGPU assembler does not set sdst correctly for GFX11 VOP3 v_cmpx instructions |
| Labels | backend:AMDGPU |
| Assignees | |
| Reporter | jayfoad |
“v_cmpx_eq_u32_e64 v12, 0” is assembled to D4CA0000 0001010C but should be D4CA007E 0001010C, because for v_cmpx instructions sdst should always be set to 0x7E (exec_lo).
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