| Issue |
61619
|
| Summary |
[ARM] `AddrMode6` operands with register offset contain additional immediate
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
Rot127
|
If an `AddrMode6` operand is decoded and the offset is given in an register (instead of an immediate), an unnecessary immediate operand is added to the disassembled `MCInst`.
Here is the code in question:
https://github.com/llvm/llvm-project/blob/7949a2a802f0791eaf7c6ecbdd6ed5daa2a278cf/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp#L2944-L2952
The decoding of `AddrMode6` operands always adds an immediate. Independently if there is one encoded in the instrucion or not.
This way the disassembled instruction is inconsistent to the defined instruction in the `.td` files.
The `MCInst`'s operand count is no longer the same as its corresponding `CodeGenInstruction`.
Which is a problem if the disassembled `MCInst` is used with generated code from `TableGen`.
**Minimal reproducable example**
- Set a breakpoint at the code above.
- Disassemble the `ARM_VLD2d32wb_register` instruction: `vld2.32 {d20, d21}, [r0], r6` (little endian: `0x864860f4`).
- See how an additional operand is added although it is not encoded in its opcode nor listed in the `In/Out OperandLists`:
Opcode of `ARM_VLD2d32wb_register` (as given by `CodeGenInstruction->TheDef->dump()`):
```
VLD2d32wb_register { // InstructionEncoding Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
...
dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, pred:$p);
...
```
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