| Issue |
64700
|
| Summary |
[RISC-V] Unexpected registers in extended inline asm
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
lekcyjna123
|
Hi,
I currently play around with kernels to test my RISC-V processor and I have found an behaviour which is unexpected for me. I have created small code sample:
```c
int main()
{
unsigned int LEN = 4;
unsigned int tab[] = {0,1,2,3};
unsigned int buf1, buf2;
// buf1 = 14;
asm volatile (
"add %[buf1], %[buf2], %[tab] \n\t"
"addi %[buf2], %[LEN], 0 \n"
: [buf1] "+r" (buf1),
[buf2] "+r" (buf2)
: [LEN]"r"(LEN),
[tab]"r"(tab)
: );
return 0;
}
```
If I create an variable without any initialisation and use it as "+r" output register with this uninitialised variable. A correct code is generated if I use clang without optimisations:
```asm
add a2, a1, a4
mv a1, a3
```
But If I use a flag for optimisations (e.g. -O2) the same registers are allocated for `buf1` `LEN` and `buf2` `tab`:
```asm
add a0, a1, a1
mv a1, a0
```
If I initialise buf* variables before inline assembly then everything is fine also with optimisations. Of course my inline assembly is buggy because I have specified that I use `buf1` and `buf2` as an input, while I don't do that, but using gcc this code compile correctly (via https://godbolt.org/z/er8PjY6xc).
So I would like to ask:
- Is the difference with gcc expected?
- Is there a possibility to warn about such issues?
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