| Issue |
71787
|
| Summary |
[RISCV] The alignment of temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node is probably 8, not 4
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
twakatsuki
|
The temporary stack introduced by the following patch causes a misalignment error when run on the Imperas OVPsim RISCV ISA simulator.
[RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node
https://reviews.llvm.org/rG9d22b54d6b214e174b786316ccc9308aa7dd7be3
Example:
```
#include <riscv_vector.h>
int main() {
size_t vl = __riscv_vsetvl_e64m1(1);
vuint64m1_t x = __riscv_vmv_v_x_u64m1(0x8000000000000000ULL, vl);
return 0;
}
```
Checked with the LLVM git main branch HEAD.
$ clang -v
clang version 18.0.0 (https://github.com/llvm/llvm-project.git b7b5907b56e98719b1dba8364ebcfb264fc09bfe)
$ clang --target=riscv32-kmc-elf -march=rv32gcv -mabi=ilp32d -S
```
main: # @main
# %bb.0:
addi sp, sp, -32
sw ra, 28(sp) # 4-byte Folded Spill
sw s0, 24(sp) # 4-byte Folded Spill
addi s0, sp, 32
csrr a0, vlenb
slli a0, a0, 1
sub sp, sp, a0
li a0, 0
sw a0, -16(s0)
vsetivli a1, 1, e64, m1, ta, ma
sw a1, -20(s0)
lw a2, -20(s0)
lui a1, 524288
sw a1, -24(s0)
sw a0, -28(s0)
addi a1, s0, -28
vsetvli zero, a2, e64, m1, ta, ma
# implicit-def: $v8
vlse64.v v8, (a1), zero
csrr a1, vlenb
slli a1, a1, 1
sub a1, s0, a1
addi a1, a1, -32
vs1r.v v8, (a1)
addi sp, s0, -32
lw ra, 28(sp) # 4-byte Folded Reload
lw s0, 24(sp) # 4-byte Folded Reload
addi sp, sp, 32
ret
```
$ riscvOVPsimPlus.exe --version
20231024.0
$ riscvOVPsimPlus.exe --variant RV32GCV --trace --tracechange --program a.out
```
...
Info 'riscvOVPsim/cpu', 0x000000008000029a(main+24): 800005b7 lui a1,0x80000
Info a1 00000001 -> 80000000
Info 'riscvOVPsim/cpu', 0x000000008000029e(main+28): feb42423 sw a1,-24(s0)
Info 'riscvOVPsim/cpu', 0x00000000800002a2(main+2c): fea42223 sw a0,-28(s0)
Info 'riscvOVPsim/cpu', 0x00000000800002a6(main+30): fe440593 addi a1,s0,-28
Info a1 80000000 -> 81ffffc4
Info 'riscvOVPsim/cpu', 0x00000000800002aa(main+34): 0d867057 vsetvli zero,a2,e64,m1,ta,ma
Info 'riscvOVPsim/cpu', 0x00000000800002ae(main+38): 0a05f407 vlse64.v v8,(a1),zero
Processor Exception (PC_PRX) Processor 'riscvOVPsim/cpu' 0x800002ae: 0a05f407 vlse64.v v8,(a1),zero
Processor Exception (PC_RAX) Misaligned 8-byte read from 0x81ffffc4
Processor Exception (PC_SED) NOTE: simulated exceptions are not enabled on processor riscvOVPsim/cpu
. If an application is being simulated that requires simulated exception support (to map memory on d
emand using an MMU, for example) please ensure simulated exceptions are enabled for correct behavior
...
```
Setting the stack alignment to 8 fixes the problem.
```
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 920657a198d9..7caa9483de6c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -92,7 +92,7 @@ void RISCVDAGToDAGISel::PreprocessISelDAG() {
// Create temporary stack for each expanding node.
SDValue StackSlot =
- CurDAG->CreateStackTemporary(TypeSize::Fixed(8), Align(4));
+ CurDAG->CreateStackTemporary(TypeSize::Fixed(8), Align(8));
int FI = cast<FrameIndexSDNode>(StackSlot.getNode())->getIndex();
MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
```
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