| Issue |
75004
|
| Summary |
Missing optimization: fold `k & c ? 0 : k & c1` to `k & !c ? 0 : c1` to remove bitmask in select arm
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
XChy
|
Alive2 proof: https://alive2.llvm.org/ce/z/Wb7Pbx
### Description:
```c
int src(bool k, bool c, bool c1) {
return k & c ? 0 : k & c1;
}
```
can be folded to:
```c
int tgt(bool k, bool c, bool c1) {
return k & ~c ? c1 : 0;
}
```
For control flow graph, it can be something like:
```llvm
define i1 @src(i32 noundef %bytes, i1 %c, i1 %c1) #0 {
entry:
%cond.not = icmp ne i32 %bytes, 0
%or.cond = and i1 %cond.not, %c
br i1 %or.cond, label %cleanup, label %land.lhs.true4
land.lhs.true4:
%or.cond20 = and i1 %cond.not, %c1
ret i1 %or.cond20
cleanup:
ret i1 0
}
; can be transformed to
define i1 @tgt(i32 noundef %bytes, i1 %c, i1 %c1) #0 {
entry:
%cond = icmp eq i32 %bytes, 0
br i1 %cond, label %cleanup, label %land.lhs.true
land.lhs.true:
br i1 %c, label %cleanup, label %land.lhs.true4
land.lhs.true4:
ret i1 %c1
cleanup:
ret i1 0
}
```
Note, we can only do such transform when there is no side-effect instructions in basic blocks.
### Real-world motivation
This snippet of IR is derived from [redis/src/config.c](https://github.com/redis/redis/blob/62419c01db4499e52ddcb689726cfa732a9736a6/src/config.c#L1272C3-L1272C3) (after O3 pipeline).
The example above is a reduced version. If you're interested in the original suboptimal IR and optimal IR, see also:https://godbolt.org/z/369xndjMa
**Let me know if you can confirm that it's an optimization opportunity, thanks.**
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