| Issue |
76072
|
| Summary |
ARM hard-float codgen issue when -Oz present
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
ltertan
|
Consider the following code:
```C
volatile float init=0;
volatile float *stage=&init;
float f1 = 0, f2 = 143;
int main()
{
f1 = *stage * 3.14;
if (f1 > 1.0F) {
f2 = 3.14F/f1;
} else {
f2 = 0.0F;
}
return 0;
}
```
When compiled with the next set of options:
```
-mhard-float --target=arm -mcpu=cortex-r52
```
It will produce valid code, as the `vdiv.f32` is inside the LBB0_1 block (as a result of the `vcmp.f32` logic)
```
vcmp.f32 s0, s2
vmrs APSR_nzcv, fpscr
ble .LBB0_2
b .LBB0_1
.LBB0_1:
movw r0, :lower16:f1
movt r0, :upper16:f1
vldr s2, [r0]
vldr s0, .LCPI0_1
vdiv.f32 s0, s0, s2
```
When compiled with the below set of options, it fails to restrict the vdiv.f32 and it may end up in a division by zero scenario:
```
-mhard-float --target=arm -mcpu=cortex-r52 -Oz
```
```
vcvt.f64.f32 d16, s0
vmul.f64 d16, d16, d17
vcvt.f32.f64 s0, d16
vcmp.f32 s0, s4
vldr s4, .LCPI0_4
vdiv.f32 s2, s2, s0
vstr s0, [r2]
```
I am able to see this behaviour on all versions between 9 and 18. Have not checked for older than 9.
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