| Issue |
83391
|
| Summary |
RVV spilling when using VCIX instructions with `-mtune=sifive-x280`
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
michalt
|
We encountered a weird problem where using `-mtune`for the X280 results in a very poor codegen: https://godbolt.org/z/qfzKMcq84 (note that by adding more blocks the problem gets worse and worse as we get more spills)
My hypothesis is that due to the recent change to allow reordering VCIX instructions, the scheduler tries to move all the loads before the VCIX instructions. What is surprising is that it doesn't seem to take into account register pressure?
@topperc and @michaelmaitland Any ideas what's happening? Thanks!
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