[llvm-bugs] [Bug 90628] [RISCV] Allow RISC-V "V" instructions in inline assembly without having to add the RVV "V" extension to command line

[LLVM Bugs via llvm-bugs]

Issue	90628
Summary	[RISCV] Allow RISC-V "V" instructions in inline assembly without having to add the RVV "V" extension to command line
Labels	new issue
Assignees
Reporter	johnplatts

    Here is a snippet of code that compiles successfully with GCC but fails to compile with Clang unless the `-march=rv32gcv1p0` or `-march=rv64gcv1p0` option is added to the command line:
```
#include <stddef.h>
#include <stdint.h>
#include <asm/hwcap.h>
#include <sys/auxv.h>

#ifndef COMPAT_HWCAP_ISA_V
#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A'))
#endif

bool IsRvv1_0Supported() {
  int64_t bits = 0;

  const unsigned long hw = getauxval(AT_HWCAP);

  if ((hw & COMPAT_HWCAP_ISA_V) == COMPAT_HWCAP_ISA_V) {
    size_t e8m1_vec_len;
#if __riscv_xlen == 64
    int64_t vtype_reg_val;
#else
    int32_t vtype_reg_val;
#endif

    // Check that a vuint8m1_t vector is at least 16 bytes and that tail
    // agnostic and mask agnostic mode are supported
    asm volatile(
 "vsetvli %0, zero, e8, m1, ta, ma\n\t"
        "csrr %1, vtype"
 : "=r"(e8m1_vec_len), "=r"(vtype_reg_val));

    // The RVV target is supported if the VILL bit of VTYPE (the MSB bit of
    // VTYPE) is not set and the length of a vuint8m1_t vector is at least 16
    // bytes
    if (vtype_reg_val >= 0 && e8m1_vec_len >= 16) {
      return true;
    }
  }

  return false;
}
```

We really want Clang to allow the above code to compile on RISC-V, even without specifying the -march=rv32gcv1p0 or -march=rv64gcv1p0 option (or another option that enables at least the RISC-V Zve32x extension), as the instructions in the inline assembly statement are only executed if the RISC-V "V" extension is present due to the check of the result returned by `getauxval(AT_HWCAP)`.

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