| Issue |
91785
|
| Summary |
Improve RISC-V Machine Outliner's ability to identify equivalent instruction sequences
|
| Labels |
enhancement,
backend:RISC-V
|
| Assignees |
|
| Reporter |
ilovepi
|
This is a work item identified in the gap analysis done in #89822.
The ARM32 backend seems to spend more time identifying equivalent instructions/instruction sequences that the outliner can take advantage of. This seems to include handling for various addressing modes.
Overall, I think the first step is to improve terminator identification and handling of tail-call transforms for RISC-V. https://github.com/llvm/llvm-project/blob/3bde7983986d8ce637f6bb506860859249787751/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp#L6004 has some basic equivalence for terminator instructions for use in when making the outlined region tail-called. In fact, it seems to me that the RISC-V implementation doesn't try very hard to use tail-call for the outlined regions. I expect that could be a major improvment on its own, and is probably either a pre-requisite for this step or is deeply coupled.
Next, we should ensure that we handle the various addressing modes in RISC-V correctly. I believe this is a bit simpler in the RISC-V backend vs. ARM, but I think we can still see an improvement w.r.t that.
Lastly, there is special handling for PIC instructions that contain labels. https://github.com/llvm/llvm-project/blob/3bde7983986d8ce637f6bb506860859249787751/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp#L6284, which I don't know if we handle at all in the RISC-V Machine outliner.
![]()
_______________________________________________
llvm-bugs mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bugs
