| Issue |
98279
|
| Summary |
[RISCV][MC] How can I get MCInst operand size?
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| Labels |
new issue
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| Assignees |
|
| Reporter |
tianboh
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Hi there, I don't know if it is right to post here, but I can't find any answer from google, so i am asking here.
I am working on a disassembling project([llvm-mctoll](https://github.com/microsoft/llvm-mctoll)) recently, and found MCInst quite useful. I need to disassemble the RISCV bytecode to LLVM IR, so basically what i am going to do first is to reconstruct function signature. Each register which is not defined before used is treated as parameter register. However, unlike x86 which can distinguish the register size by its prefix (%rax, %eax, %ax, etc,.), RISCV seems use the whole register.
Based on the RISCV Spec base ISA opcode map, I classified the instructions to three types: Load/Store, Algo, Algo-Op-Imm-32. For load/store, the instruction will tell the size it processes. For Algo, the instruction will use the whole register based on its ISA. For algo-op-imm-32, which is basically ISA 64G, it uses 32 bit of registers.
However, thing gets complicated when taking C extension into consideration. I cannot easily classify the instructions like before. I am wondering if I can get any access size information from `MCInst`, or `MachineInstr` classes? I know there is a `Operand` class and `MachineOperand` class, but like I said, some instructions record the size thet're going to access(load/store), this size information should be found in the instructions.
Please correct me if I am wrong or missing anything, any suggestions are welcome!
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