| Issue |
109391
|
| Summary |
[AMDGPU] Identical LLVM IR file with different basic block ordering cause miscompilation
|
| Labels |
backend:AMDGPU,
miscompilation,
julialang
|
| Assignees |
|
| Reporter |
vchuravy
|
Reduced from https://github.com/JuliaGPU/AMDGPU.jl/issues/672#issuecomment-2347151487
The code is a double-nested loops and the bug manifests as if we were skipping a loop.
In one version of the code after optimization (specifically DCE) the basic blocks end up in a different order.
I have two small LLVM modules that are identical, except that in one I manually reorder the BBs to follow the order of the "working" version.
https://godbolt.org/z/sscdTK7d7
https://gist.github.com/vchuravy/0c60cf4b9c497f6c8050f2a1137cd399
```
llc -filetype=asm broken.reorder.ll -o broken.reorder.S
llc -filetype=asm broken.ll -o broken.S
```
`broken.ll` is the original file that is exhibiting the miscompiation and `broken.reorder.ll` is the file that emits the same code as the working MWE.
Lastly, I encountered this on LLVM 15, and it also reproduces on LLVM 16. LLVM 17 either hides or has this bug fixed.
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