| Issue |
114282
|
| Summary |
AMDGPU does not avoid clamp of bit shift in BFE pattern
|
| Labels |
backend:AMDGPU,
missed-optimization
|
| Assignees |
changpeng
|
| Reporter |
arsenm
|
https://godbolt.org/z/nT9dMvrxv
```
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s
define i32 @bfe(i32 %scr0, i32 %src1) {
%src2.clamp.i = and i32 %src1, 31
%shl.src2.i = shl i32 1, %src2.clamp.i
%rhs.i = sub i32 %shl.src2.i, 1
%and.i = and i32 %scr0, %rhs.i
ret i32 %and.i
}
```
This fails to eliminate the and clamping the shift size. The instruction only reads the low 5 bits, so we can erase the and.
```
bfe: ; @bfe
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
v_and_b32_e32 v1, 31, v1
v_bfe_u32 v0, v0, 0, v1
s_setpc_b64 s[30:31]
.Lfunc_end0:
```
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