| Issue |
115640
|
| Summary |
Why does llc compile direct calls to RISCV interrupts?
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
workingjubilee
|
The following code compiles:
```llvm
source_filename = "example.925e6eb0586113f0-cgu.0"
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"
define void @_ZN7example17interrupt_machine17h9aedfc539b69d0e4E() unnamed_addr #0 {
ret void
}
define void @_ZN7example20interrupt_supervisor17h3af0168b331d21a0E() unnamed_addr #1 {
ret void
}
define void @_ZN7example4main17h90b0fda4f240e4d2E() unnamed_addr #2 {
call void @_ZN7example17interrupt_machine17h9aedfc539b69d0e4E() #3
call void @_ZN7example20interrupt_supervisor17h3af0168b331d21a0E() #3
ret void
}
attributes #0 = { nounwind uwtable "interrupt"="machine" "target-cpu"="generic-rv64" "target-features"="+m,+a,+f,+d,+c" }
attributes #1 = { nounwind uwtable "interrupt"="supervisor" "target-cpu"="generic-rv64" "target-features"="+m,+a,+f,+d,+c" }
attributes #2 = { uwtable "target-cpu"="generic-rv64" "target-features"="+m,+a,+f,+d,+c" }
attributes #3 = { nounwind }
!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}
!0 = !{i32 8, !"PIC Level", i32 2}
!1 = !{i32 1, !"Code Model", i32 3}
!2 = !{i32 1, !"target-abi", !"lp64d"}
!3 = !{!"rustc version 1.84.0-nightly (b91a3a056 2024-11-07)"}
```
It seems like it should not, given that this code does not compile:
```llvm
source_filename = "example.925e6eb0586113f0-cgu.0"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
define x86_intrcc void @_ZN7example13lol_interrupt17h978ba38488afd6e7E() unnamed_addr #0 {
ret void
}
define void @_ZN7example4main17h90b0fda4f240e4d2E() unnamed_addr #1 {
call x86_intrcc void @_ZN7example13lol_interrupt17h978ba38488afd6e7E() #2
ret void
}
attributes #0 = { nounwind nonlazybind uwtable "probe-stack"="inline-asm" "target-cpu"="x86-64" }
attributes #1 = { nonlazybind uwtable "probe-stack"="inline-asm" "target-cpu"="x86-64" }
attributes #2 = { nounwind }
!llvm.module.flags = !{!0, !1}
!llvm.ident = !{!2}
!0 = !{i32 8, !"PIC Level", i32 2}
!1 = !{i32 2, !"RtLibUseGOT", i32 1}
!2 = !{!"rustc version 1.84.0-nightly (b91a3a056 2024-11-07)"}
```
Of course, x86 is uniquely "quirky", especially on interrupt entry. I'm not aware if this is... conceptually valid? ...for RISCV, so feel free to close this if this is truly intentional.
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