| Issue |
115697
|
| Summary |
Missed optimisation to take advantage of commutative SVE fmul instruction
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
ktkachov
|
Example AArch64 SVE intrinsics code:
```
#include <arm_sve.h>
svfloat64_t svmul_x_2(svfloat64_t x, svfloat64_t y, svbool_t pg)
{
return svmul_x(pg, svdup_f64(2), x);
}
```
This can generate just a singly FMUL instruction but LLVM moves the immediate 2 into a register first.
https://godbolt.org/z/11aEEGoce
![]()
_______________________________________________
llvm-bugs mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bugs
