| Issue |
126781
|
| Summary |
[AMDGPU] getSubRegs in SIRegisterInfo.td can be simplified
|
| Labels |
|
| Assignees |
|
| Reporter |
jurahul
|
It seems the code is essentially slicing a large list using conditions, can be simplified to an assert (for size check) and a list slice, using the `ret32` list and size.
Simple starter task for someone interested in TD files. Verify that the generated GenRegInfo file is the same before/after the fix.
![]()
_______________________________________________
llvm-bugs mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bugs
