| Issue |
134663
|
| Summary |
[ARM32][compiler-rt] movle Condition Fails After __aeabi_cdcmple Due to Inconsistent CPSR Flags Across libgcc/libunwind
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
dongjianqiang2
|
Hi, I compiled the Luajit with clang, and found the __aeabi_cdcmple fails to set CPSR Flags correctly for movle insn.
https://github.com/LuaJIT/LuaJIT/blob/v2.1/src/vm_arm.dasc#L1705
```
#include <stdio.h>
#include <stdint.h>
extern void __aeabi_cdcmple(double a, double b);
void test_with_movle() {
uint32_t cpsr;
uint32_t r0_val, r1_val;
__asm__ __volatile__(
// Set initial register values
"mov r0, #0x0\n\t" // a_low = 0x0
"ldr r1, =0xBFF00000\n\t" // a_high = 0xBFF00000 → a = -1.0
"mov r2, #0x1\n\t" // b_low = 0x1
"ldr r3, =0x40000000\n\t" // b_high = 0x40000000 → b = 2.0
// Call comparison function (modifies CPSR)
"bl __aeabi_cdcmple\n\t"
// Conditional move: if a <= b (LE condition true), r0 = r2, r1 = r3
"movle r0, r2\n\t" // If LE, move b_low to r0
"movle r1, r3\n\t" // If LE, move b_high to r1
// Save registers to variables
"mov %0, r0\n\t" // Save r0 to r0_val
"mov %1, r1\n\t" // Save r1 to r1_val
"mrs %2, cpsr\n\t" // Save CPSR
: "=r" (r0_val), "=r" (r1_val), "=r" (cpsr)
:
: "r0", "r1", "r2", "r3", "lr", "cc", "memory"
);
// Extract CPSR flags
int N = (cpsr >> 31) & 1; // Bit 31: N (Negative)
int Z = (cpsr >> 30) & 1; // Bit 30: Z (Zero)
int C = (cpsr >> 29) & 1; // Bit 29: C (Carry)
int V = (cpsr >> 28) & 1; // Bit 28: V (Overflow)
// Print results
printf("After movle:\n");
printf("r0 = 0x%08X, r1 = 0x%08X\n", r0_val, r1_val);
printf("Flags: N=%d, Z=%d, C=%d, V=%d\n", N, Z, C, V);
}
int main() {
test_with_movle();
return 0;
}
```
gcc with libgcc：
After movle:
r0 = 0x00000001, r1 = 0x40000000
Flags: N=1, Z=0, C=0, V=0
clang with compiler-rt:
After movle:
r0 = 0x00000000, r1 = 0xBFF00000
Flags: N=0, Z=0, C=0, V=0
Is this a compatibility issue between Clang and GCC?
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