| Issue |
137892
|
| Summary |
[SPIR-V] Legalize the `llvm.is.fpclass` intrinsic
|
| Labels |
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| Assignees |
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| Reporter |
Icohedron
|
## Description
LLVM Language Reference: [`llvm.is.fpclass`](https://llvm.org/docs/LangRef.html#llvm-is-fpclass-intrinsic)
The lowering of `llvm.is.fpclass` depends on the compile-time constant operand `i32 <test>`.
Valid bits for `<test>` are defined in an enum named [FPClassTest](https://github.com/llvm/llvm-project/blob/dd2a1590c34d250b70de6d9a4a11b9a13aacb8ac/llvm/include/llvm/ADT/FloatingPointMode.h#L237-L265).
The following FPClassTest cases are of interest:
- `FPClassTest::fcInf`, `FPClassTest::fcNan`, `FPClassTest::fcFinite`, `FPClassTest::fcNormal` map directly to SPIR-V Ops
The lowering of `llvm.is.fpclass` to both SPIR-V and [DirectX](https://github.com/llvm/llvm-project/issues/137209) will simplify the codegen for HLSL intrinsics [`isinf`](https://github.com/llvm/llvm-project/issues/70095), [`isnan`](https://github.com/llvm/llvm-project/issues/99132), and [`isfinite`](https://github.com/llvm/llvm-project/issues/99131)
### SPIRV Ops
- `OpIsInf`
- `OpIsNan`
- `OpIsNormal`
- `OpIsFinite`
Note: The [SPIRV specification](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html) states that the results of these ops depends on the floating-point encoding used. However, there are currently no alternative floating-point encodings listed in the specification.
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