| Issue |
142677
|
| Summary |
[HLSL][SPIRV] Handle 16/64-bit versions of `countbits`
|
| Labels |
clang:HLSL:SPIRV
|
| Assignees |
|
| Reporter |
inbelic
|
https://godbolt.org/z/cb9KGh5Eq
As shown in the reproduction case, we will generate an `OpBitCount` with 16/64-bit width types.
However, as denoted [here](https://vulkan.lunarg.com/doc/view/1.4.313.1/windows/antora/spec/latest/appendices/spirvenv.html#VUID-StandaloneSpirv-Base-04781), the SPIR-V validator will only accept these arguments to have a type of 32-bit width.
Note: This is in contrast to the SPIR-V `OpBitCount` specification that denotes the Result and Base type can be a scalar or vector of integer type.
As such, the expected behaviour should be such that it will emulate the operation for the non 32-bit types.
AC:
- Update lowering of `bitcount` intrinsic to emulate the non 32-bit operations similar to `firstbitlow` and `firstbithight`
- Add sufficient test cases, this may depend on: https://github.com/llvm/llvm-project/issues/142669.
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