| Issue |
166563
|
| Summary |
[AArch64][GISel] ANDXrr "Expected a GPR64 register, but got a GPR64sp register"
|
| Labels |
backend:AArch64,
llvm:globalisel
|
| Assignees |
|
| Reporter |
sjoerdmeijer
|
This IR that is most like not minimal:
```
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "aarch64-unknown-linux-gnu"
define i64 @_Z4testajhhsxibxjxhsiPxPsPA15_iPA15_jPbPyS5_PA20_sPA20_A20_yPA20_A20_iPA20_A20_xPhSI_PA20_S7_SE_PA20_A20_jSH_SN_S8_SH_SB_PA20_A20_h(i1 %var_7) {
entry:
%tobool.not = icmp eq i8 0, 0
br i1 %tobool.not, label %entry.split.us.split.us.split.us.split.us, label %for.body.us.us993.us
entry.split.us.split.us.split.us.split.us: ; preds = %entry
br i1 %var_7, label %for.body19.us.us.us.us.us.us.us.us.us, label %for.body.us.us.us.us.preheader
for.body.us.us.us.us.preheader: ; preds = %entry.split.us.split.us.split.us.split.us
%unroll_iter1523 = and i64 0, 457873110
ret i64 %unroll_iter1523
for.body19.us.us.us.us.us.us.us.us.us: ; preds = %for.body19.us.us.us.us.us.us.us.us.us, %entry.split.us.split.us.split.us.split.us
%niter1529 = phi i64 [ %niter1529.next.1, %for.body19.us.us.us.us.us.us.us.us.us ], [ 0, %entry.split.us.split.us.split.us.split.us ]
%niter1529.next.1 = add i64 %niter1529, 1
%niter1529.ncmp.1 = icmp eq i64 %niter1529, 457873108
br label %for.body19.us.us.us.us.us.us.us.us.us
for.body.us.us993.us: ; preds = %for.body19.us.us967.us.us.us.us, %entry
%0 = load i16, ptr null, align 2
br label %for.body19.us.us967.us.us.us.us
for.body19.us.us967.us.us.us.us: ; preds = %for.body19.us.us967.us.us.us.us, %for.body.us.us993.us
%cmp17.us.us990.us.us.us.us = icmp ult i64 0, 457873110
br i1 %cmp17.us.us990.us.us.us.us, label %for.body19.us.us967.us.us.us.us, label %for.body.us.us993.us
}
```
Triggers this verifier failure:
```
*** Bad machine code: Illegal virtual register for instruction ***
- function: _Z4testajhhsxibxjxhsiPxPsPA15_iPA15_jPbPyS5_PA20_sPA20_A20_yPA20_A20_iPA20_A20_xPhSI_PA20_S7_SE_PA20_A20_jSH_SN_S8_SH_SB_PA20_A20_h
- basic block: %bb.5 for.body.us.us.us.us.preheader (0xaaaab01c71f0)
- instruction: %13:gpr64 = ANDXrr %24:gpr64, %6:gpr64sp
- operand 2: %6:gpr64sp
Expected a GPR64 register, but got a GPR64sp register
```
See also: https://godbolt.org/z/1sPdG5976
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