| Issue |
171992
|
| Summary |
[X86][GlobalIsel] GISEL does not have Post-Isel Register Constraining
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
mahesh-attarde
|
While doing https://github.com/llvm/llvm-project/pull/165848 I encountered case which needs better engineering fix.
GISEL Input
```
bb.1.entry:
%4:gpr(s32) = G_CONSTANT i8 0
$al = COPY %4(sub_reg:gr32)
RET 0, implicit $al
```
Exact GISEL Failure:
```
# After InstructionSelect
# Machine code for function isnone_f: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
bb.1.entry:
%5:gr32 = MOV32r0 implicit-def dead $eflags
%4:gr8 = COPY %5.sub_8bit:gr32
$al = COPY %4:gr8
RET 0, implicit $al
*** Bad machine code: Invalid register class for subregister index ***
- function: isnone_f
- basic block: %bb.1 entry (0x5e1917110858)
- instruction: %4:gr8 = COPY %5.sub_8bit:gr32
- operand 1: %5.sub_8bit:gr32
Register class GR32 does not fully support subreg index sub_8bit
LLVM ERROR: Found 1 machine code errors.
```
Idea here is since %4 is 8 bit use of %4 should be constraint to regclass with subregister index, e.g. GR32_ABCD in current case.
We could not constraint it before ISEL because pattern does not have constraint and it would fail to match. DAG did similar work post-isel, post-scheduling in Inst Emitter, All COPY instructions with SUB_REG nodes have imposed constraints.
We done similar
DAG Output - Post Isel
```
bb.0.entry:
%0:gr32_abcd = MOV32r0 implicit-def dead $eflags
%1:gr8 = COPY %0.sub_8bit:gr32_abcd
$al = COPY %1:gr8
RET 0, $al
```
Since InstEmitter changes were in generic infra, I tried similar mechanism https://github.com/llvm/llvm-project/pull/165848/commits/daa40d0e09550919598aa8e0af0eb29fd01051bb
Other solution of doing Pre-Isel Manual handing for G_CONSTANT is still no good considering we defer pattern tables for many tests.
We may need to revisit this problem again since gisel combiner also hits same error.
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