| Issue |
178600
|
| Summary |
RISC-V srliw regression after #164946
|
| Labels |
backend:RISC-V
|
| Assignees |
|
| Reporter |
lukel97
|
After #164946 we no longer select srliw for this:
```llvm
define i32 @bittest_31_slt0_i32(i32 %x, i1 %y) {
; RV64-LABEL: bittest_31_slt0_i32:
; RV64: # %bb.0:
; RV64-NEXT: slli a0, a0, 32 1
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: ret
%cmp = icmp slt i32 %x, 0
%and = and i1 %cmp, %y
%ext = zext i1 %and to i32
ret i32 %ext
}
```
![]()
_______________________________________________
llvm-bugs mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bugs
