| Issue |
179672
|
| Summary |
[WebAssembly][FastISel] Inquiry regarding redundant extension logic after sub-word loads (i8, i16)
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
ParkHanbum
|
Context & Observation
While analyzing the output of WebAssemblyFastISel, I noticed that explicit sign/zero extension sequences are generated even when the value originates directly from a sub-word load instruction (e.g., i8 or i16).
Current Output (Example: i16 load -> sext)
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