| Issue |
180831
|
| Summary |
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32
|
| Labels |
enhancement,
backend:RISC-V
|
| Assignees |
|
| Reporter |
lenary
|
Our calling convention handling splits 64-bit values into two 32-bit values, before assigning them to a pair of registers (potentially not a GPRPair). Register coalescing looks through COPYs and can end up splitting a COPY of GPRPairs into two COPYs of the GPR sub-regs.
This means there's quite a few places in our tests where we end up with:
```
mv a0, xN
mv a1, x(N+1)
```
With either Zdinx (`fmv.d`) or P (`addd`), we could transform this to a single instruction that moves both registers at once. We already have a pass to do this for Zcmp (and Xqccmp) -- the RISC-V Move Merger -- but only for `cm.mva01s` and `cm.mvsa01`, which have other restrictions the two registers being moved.
(This approach means we don't change how registers are allocated/coalesced, which should mean we can still end up with two `mv`s when the register allocator tells us it's better the registers aren't allocated into an even-odd pair. We don't want to over-constrain allocation.)
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