| Issue |
183104
|
| Summary |
InstCombine scalarizes aligned vector load to unaligned scalar load on RISC-V
|
| Labels |
backend:RISC-V,
llvm:instcombine
|
| Assignees |
|
| Reporter |
lukel97
|
This is probably directly related to #180617
On RISC-V, vector loads and stores are element aligned, so the following load is aligned:
```llvm
define i64 @foo(ptr %p) {
%v = load <4 x i16>, ptr %p, align 2
%x = bitcast <4 x i16> %v to i64
ret i64 %x
}
```
But InstCombine will scalarize this to an unaligned load:
```llvm
define i64 @foo(ptr %p) #0 {
%v1 = load i64, ptr %p, align 2
ret i64 %v1
}
```
https://godbolt.org/z/1s9qEPhz4
I'm guessing that InstCombine sees both loads as unaligned so it goes ahead with the transform. But we should be specifying in the datalayout that the vector load is actually aligned.
Although the following load comes from SLP, which must have some more information that the vector load is aligned. Probably from TTI?
Found from regressions after #182684
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