| Issue |
183768
|
| Summary |
[AArch64] Can we use legal vXi8 CLMUL to improve vXi16/vXi32/Xi64 CLMUL codegen
|
| Labels |
backend:AArch64
|
| Assignees |
|
| Reporter |
RKSimon
|
https://github.com/llvm/llvm-project/blob/2265d3240f23c1c6ff7b4d0fa2711a9ed36fdc8a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp#L5483-L5506
Can we reuse the ExpandIntRes_CLMUL pattern to help aarch64 vXi16/vXi32/Xi64 CLMUL codegen by using vXi8 clmul support to create lo/hi halves for merging
Preferably this needs to be done generically but it might have to be done in AArch64ISelLowering
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