| Issue |
185382
|
| Summary |
[CIR] Upstream handling of AArch64 (Arm) Neon builtins
|
| Labels |
new issue,
ClangIR
|
| Assignees |
|
| Reporter |
banach-space
|
### Overview
This is an umbrella issue for upstreaming all AArch64 builtins to ClangIR.
There are enough AArch64-specific builtins that creating separate issues for each logical group is not practical. Multiple contributors can work on this in parallel, provided we coordinate to minimize overlap. To help with that, a partial list of builtins that need to be upstreamed is included below.
If you would like to contribute, please comment indicating which builtin(s) you plan to work on.
Builtins will be removed from this list as they are upstreamed.
Before beginning work, please check the table below to ensure no one else is already working on the same intrinsics. If you have any questions, please comment here and tag @banach-space.
### Needed builtins
| Intrinsic Group | Common prefix | Assignee | PR(s) | Status |
|-------------------------|---------------|----------|-------|--------|
| [Set vector lane](https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#set-vector-lane) | `vset_lane_*`, `vsetq_lane_*` | | | (*) `vset_lane_i8` ... |
| [Extract one element from vector](https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#extract-one-element-from-vector) | `vget_lane_*`, `vgetq_lane_*` | | | (*) `vget_lane_i8` ... |
| [Vector saturating shift left](https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-saturating-shift-left) | `vqshl_*` | | | (*) `vqshlud_n_s64`, `vqshld_n_u64`, `vqshld_n_s64` |
| [Vector rounding shift right](https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-rounding-shift-right) | `vrshr_*` | | | (*) `vrshrd_n_u64`, `vrshrd_n_s64` |
| [Vector rounding shift right and accumulate](https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-rounding-shift-right-and-accumulate) | `vrsra_*` | | | (*) `vrsrad_n_u64`, `vrsrad_n_s64` |
| [Vector shift left](https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-left) | `vshl_*` | | | (*) `vshld_n_s64`, `vshld_n_u64` |
| [Vector shift right](https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-right) | `vshr_*` | | | (*) `vshrd_n_s64`, `vshrd_n_u64` |
| [Split vectors (BFloat16)](https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#split-vectors-1) | `vget{q}_lane_bf16` | | | (*) `vget_lane_bf16`, `vgetq_lane_bf16` |
| [Set all lanes to the same value (BFloat16)](https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#set-all-lanes-to-the-same-value-2) | `vduph_lane{q}_bf16` | | | (*) `vduph_lane_bf16`, `vduph_laneq_bf16` |
| [Set all lanes to the same value (FP16)](https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#set-all-lanes-to-the-same-value-1) | `vdup*_f16` | | | (*) `vduph_lane_f16`, `vduph_laneq_f16` |
| [Scalar & vector intrinsics (FP16)](https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#fp16-scalar-intrinsics-available-through--from-armv82-a) | `v*_f16` | | | (*) `vaddh_f16`, `vsubh_f16`, `vmulh_f16`, `vdivh_f16` |
(*) Special cases are implemented in [CIRGenFunction::emitAArch64BuiltinExpr](https://github.com/llvm/clangir/blob/main/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp#L3390) in the ClangIR incubator repository - these are usually the easiest starting point.
### Implementation requirements
1. For each intrinsic group listed in the [Arm Neon Intrinsics Reference](https://arm-software.github.io/acle/neon_intrinsics/advsimd.html), ensure that **all variants are supported and tested**. If some variants are missing in the [ClangIR incubator repository](https://github.com/llvm/clangir), please implement them.
2. **Reuse the existing AArch64 builtin tests** located in [clang/test/CodeGen/AArch64](https://github.com/llvm/llvm-project/tree/main/clang/test/CodeGen/AArch64). These tests will need to be moved to the [neon subdirectory](https://github.com/llvm/llvm-project/tree/main/clang/test/CodeGen/AArch64/neon), which enables ClangIR testing. For more context, see: https://github.com/llvm/llvm-project/issues/179952.
3. Tests should follow the format used in [intrinsics.c](https://github.com/llvm/llvm-project/blob/main/clang/test/CodeGen/AArch64/neon/intrinsics.c).
### References
* Previous umbrella tickets for X86: https://github.com/llvm/llvm-project/issues/167752 + https://github.com/llvm/llvm-project/issues/167765
* Neon overviews: https://www.arm.com/technologies/neon + https://developer.arm.com/Architectures/Neon
* Neon ACLE: https://arm-software.github.io/acle/neon_intrinsics/
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