| Issue |
203610
|
| Summary |
[AMDGPU] Properly fix WAR hazard for SMEM load followed by VMEM store
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
jayfoad
|
[D71934](https://reviews.llvm.org/D71934) inserted a wait between an SMEM load and a following VMEM store but only if the IR values for the memory addresses are identical. For correctness it should be done whenever the compiler cannot prove that the load and the store do not alias.
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