Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.20 -> 1.21 X86InstrInfo.td updated: 1.187 -> 1.188 --- Log message: Added ConstantFP patterns. --- Diffs of the changes: (+33 -31) X86ISelDAGToDAG.cpp | 27 --------------------------- X86InstrInfo.td | 37 +++++++++++++++++++++++++++++++++---- 2 files changed, 33 insertions(+), 31 deletions(-) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.20 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.21 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.20 Wed Jan 4 18:27:02 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Jan 4 20:08:37 2006 @@ -410,33 +410,6 @@ return CodeGenMap[N] = CurDAG->getTargetNode(Opc, VT, Result); break; } - - case ISD::ConstantFP: { - Opc = 0; - if (X86ScalarSSE) { - assert(cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0) && - "SSE only supports +0.0"); - Opc = (NVT == MVT::f32) ? X86::FLD0SS : X86::FLD0SD; - } - - if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0) || - cast<ConstantFPSDNode>(N)->isExactlyValue(-0.0)) - Opc = X86::FpLD0; - else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0) || - cast<ConstantFPSDNode>(N)->isExactlyValue(-1.0)) - Opc = X86::FpLD1; - - assert(Opc != 0 && "Unexpected constant!"); - - SDOperand Result = CurDAG->getTargetNode(Opc, NVT); - - if (cast<ConstantFPSDNode>(N)->getValue() < 0.0 || - cast<ConstantFPSDNode>(N)->isExactlyValue(-0.0)) - Result = CurDAG->getTargetNode(X86::FpCHS, NVT, Result); - - CodeGenMap[N] = Result; - return Result; - } } return SelectCode(N); Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.187 llvm/lib/Target/X86/X86InstrInfo.td:1.188 --- llvm/lib/Target/X86/X86InstrInfo.td:1.187 Wed Jan 4 18:27:02 2006 +++ llvm/lib/Target/X86/X86InstrInfo.td Wed Jan 4 20:08:37 2006 @@ -244,6 +244,26 @@ return (unsigned)N->getValue() == (unsigned char)N->getValue(); }]>; +def fp32imm0 : PatLeaf<(f32 fpimm), [{ + return N->isExactlyValue(+0.0); +}]>; + +def fp64imm0 : PatLeaf<(f64 fpimm), [{ + return N->isExactlyValue(+0.0); +}]>; + +def fp64immneg0 : PatLeaf<(f64 fpimm), [{ + return N->isExactlyValue(-0.0); +}]>; + +def fp64imm1 : PatLeaf<(f64 fpimm), [{ + return N->isExactlyValue(+1.0); +}]>; + +def fp64immneg1 : PatLeaf<(f64 fpimm), [{ + return N->isExactlyValue(-1.0); +}]>; + // Helper fragments for loads. def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>; @@ -2187,9 +2207,13 @@ // Pseudo-instructions that map fld0 to xorps/xorpd for sse. // FIXME: remove when we can teach regalloc that xor reg, reg is ok. def FLD0SS : I<0x57, MRMSrcReg, (ops FR32:$dst), - "xorps $dst, $dst", []>, Requires<[HasSSE1]>, TB; + "xorps $dst, $dst", + [(set FR32:$dst, fp32imm0)]>, + Requires<[HasSSE1]>, TB; def FLD0SD : I<0x57, MRMSrcReg, (ops FR64:$dst), - "xorpd $dst, $dst", []>, Requires<[HasSSE2]>, TB, OpSize; + "xorpd $dst, $dst", + [(set FR64:$dst, fp64imm0)]>, + Requires<[HasSSE2]>, TB, OpSize; let isTwoAddress = 1 in { // SSE Scalar Arithmetic @@ -2568,8 +2592,13 @@ def FXCH : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9; // Floating point constant loads. -def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP, []>; -def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP, []>; +def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP, + [(set RFP:$dst, fp64imm0)]>; +def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP, + [(set RFP:$dst, fp64imm1)]>; + +def : Pat<(f64 fp64immneg0), (FpCHS (FpLD0))>, Requires<[FPStack]>; +def : Pat<(f64 fp64immneg1), (FpCHS (FpLD1))>, Requires<[FPStack]>; def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9; def FLD1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9; _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits