[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp

[Duraid Madina]

Changes in directory llvm/lib/Target/IA64:

IA64ISelLowering.cpp updated: 1.22 -> 1.23
---
Log message:

fix calls that return f32



---
Diffs of the changes:  (+7 -2)

 IA64ISelLowering.cpp |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.22 
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.23
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.22      Sun Jan 15 03:45:23 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp   Thu Jan 19 02:31:51 2006
@@ -473,7 +473,7 @@
   SDOperand RetVal;
   if (RetTyVT != MVT::isVoid) {
     switch (RetTyVT) {
-    default: // assert(0 && "Unknown value type to return!");
+    default: assert(0 && "Unknown value type to return!");
     case MVT::i1: { // bools are just like other integers (returned in r8)
       SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, 
InFlag);
       InFlag = boolInR8.getValue(2);
@@ -491,7 +491,7 @@
       RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
       Chain = RetVal.getValue(1);
       
-      // Add a note to keep track of whether it is sign or zero extended - 
TODO: bools
+      // keep track of whether it is sign or zero extended (todo: bools?)
       RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext 
:ISD::AssertZext,
                            MVT::i64, RetVal, DAG.getValueType(RetTyVT));
       RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
@@ -501,6 +501,11 @@
       Chain = RetVal.getValue(1);
       InFlag = RetVal.getValue(2); // XXX dead
       break;
+    case MVT::f32:
+      RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
+      Chain = RetVal.getValue(1);
+      RetVal = DAG.getNode(ISD::TRUNCATE, MVT::f32, RetVal);
+      break;
     case MVT::f64:
       RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
       Chain = RetVal.getValue(1);



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