Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.62 -> 1.63 SelectionDAGISel.cpp updated: 1.148 -> 1.149 --- Log message: Add initial support for immediates. This allows us to compile this: int %rlwnm(int %A, int %B) { %C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17) ret int %C } into: _rlwnm: or r2, r3, r3 or r3, r4, r4 rlwnm r2, r2, r3, 4, 17 ;; note the immediates :) or r3, r2, r2 blr --- Diffs of the changes: (+16 -6) ScheduleDAG.cpp | 20 +++++++++++++++----- SelectionDAGISel.cpp | 2 +- 2 files changed, 16 insertions(+), 6 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.62 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.63 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.62 Tue Jan 31 16:23:14 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Fri Feb 3 20:26:14 2006 @@ -300,16 +300,26 @@ // Add all of the operand registers to the instruction. for (unsigned i = 2; i != NumOps; i += 2) { - unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); unsigned Flags =cast<ConstantSDNode>(Node->getOperand(i+1))->getValue(); MachineOperand::UseType UseTy; switch (Flags) { default: assert(0 && "Bad flags!"); - case 1: UseTy = MachineOperand::Use; break; - case 2: UseTy = MachineOperand::Def; break; - case 3: UseTy = MachineOperand::UseAndDef; break; + case 1: { // Use of register. + unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); + MI->addMachineRegOperand(Reg, MachineOperand::Use); + break; + } + case 2: { // Def of register. + unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); + MI->addMachineRegOperand(Reg, MachineOperand::Def); + break; + } + case 3: { // Immediate. + uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue(); + MI->addZeroExtImm64Operand(Val); + break; + } } - MI->addMachineRegOperand(Reg, UseTy); } break; } Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.148 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.149 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.148 Fri Feb 3 20:16:44 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Feb 3 20:26:14 2006 @@ -1366,7 +1366,7 @@ // Add information to the INLINEASM node to know about this input. AsmNodeOperands.push_back(ResOp); - AsmNodeOperands.push_back(DAG.getConstant(1, MVT::i32)); // ISUSE + AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); break; } case InlineAsm::isClobber: _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits