Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.156 -> 1.157 X86ISelLowering.h updated: 1.50 -> 1.51 X86InstrSSE.td updated: 1.61 -> 1.62 --- Log message: Handle canonical form of e.g. vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7> This is turned into vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3> by dag combiner. It would match a {p}unpckl on x86. --- Diffs of the changes: (+56 -0) X86ISelLowering.cpp | 33 +++++++++++++++++++++++++++++++++ X86ISelLowering.h | 5 +++++ X86InstrSSE.td | 18 ++++++++++++++++++ 3 files changed, 56 insertions(+) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.156 llvm/lib/Target/X86/X86ISelLowering.cpp:1.157 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.156 Wed Apr 5 01:11:20 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Apr 5 02:20:06 2006 @@ -1664,6 +1664,37 @@ return true; } +/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form +/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, +/// <0, 0, 1, 1> +bool X86::isUNPCKL_v_undef_Mask(SDNode *N) { + assert(N->getOpcode() == ISD::BUILD_VECTOR); + + unsigned NumElems = N->getNumOperands(); + if (NumElems != 4 && NumElems != 8 && NumElems != 16) + return false; + + for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { + SDOperand BitI = N->getOperand(i); + SDOperand BitI1 = N->getOperand(i+1); + + if (BitI.getOpcode() != ISD::UNDEF) { + assert(isa<ConstantSDNode>(BitI) && "Invalid VECTOR_SHUFFLE mask!"); + if (cast<ConstantSDNode>(BitI)->getValue() != j) + return false; + } + + if (BitI1.getOpcode() != ISD::UNDEF) { + assert(isa<ConstantSDNode>(BitI1) && "Invalid VECTOR_SHUFFLE mask!"); + if (cast<ConstantSDNode>(BitI1)->getValue() != j) + return false; + } + } + + return true; +} + + /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies /// a splat of a single element. bool X86::isSplatMask(SDNode *N) { @@ -2604,6 +2635,7 @@ } if (X86::isUNPCKLMask(PermMask.Val) || + X86::isUNPCKL_v_undef_Mask(PermMask.Val) || X86::isUNPCKHMask(PermMask.Val)) // Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*. return Op; @@ -2929,5 +2961,6 @@ isPSHUFHW_PSHUFLWMask(Mask.Val) || X86::isSHUFPMask(Mask.Val) || X86::isUNPCKLMask(Mask.Val) || + X86::isUNPCKL_v_undef_Mask(Mask.Val) || X86::isUNPCKHMask(Mask.Val)); } Index: llvm/lib/Target/X86/X86ISelLowering.h diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.50 llvm/lib/Target/X86/X86ISelLowering.h:1.51 --- llvm/lib/Target/X86/X86ISelLowering.h:1.50 Fri Mar 31 15:55:24 2006 +++ llvm/lib/Target/X86/X86ISelLowering.h Wed Apr 5 02:20:06 2006 @@ -220,6 +220,11 @@ /// specifies a shuffle of elements that is suitable for input to UNPCKH. bool isUNPCKHMask(SDNode *N); + /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form + /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, + /// <0, 0, 1, 1> + bool isUNPCKL_v_undef_Mask(SDNode *N); + /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a splat of a single element. bool isSplatMask(SDNode *N); Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.61 llvm/lib/Target/X86/X86InstrSSE.td:1.62 --- llvm/lib/Target/X86/X86InstrSSE.td:1.61 Tue Apr 4 16:49:39 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 5 02:20:06 2006 @@ -100,6 +100,10 @@ return X86::isUNPCKHMask(N); }]>; +def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{ + return X86::isUNPCKL_v_undef_Mask(N); +}]>; + def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{ return X86::isPSHUFDMask(N); }], SHUFFLE_get_shuf_imm>; @@ -1733,6 +1737,20 @@ (v4f32 (PSHUFLWmi addr:$src1, PSHUFLW_fp_shuffle_mask:$sm))>, Requires<[HasSSE2]>; +// vector_shuffle v1, <undef>, <0, 0, 1, 1, ...> +def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), + UNPCKL_v_undef_shuffle_mask)), + (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; +def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef), + UNPCKL_v_undef_shuffle_mask)), + (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; +def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef), + UNPCKL_v_undef_shuffle_mask)), + (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; +def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef), + UNPCKL_v_undef_shuffle_mask)), + (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>; + // 128-bit logical shifts def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2), (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>; _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits