Changes in directory llvm/lib/Target/Sparc:
FPMover.cpp updated: 1.12 -> 1.13 SparcRegisterInfo.cpp updated: 1.42 -> 1.43 --- Log message: Move some methods out of MachineInstr into MachineOperand --- Diffs of the changes: (+6 -7) FPMover.cpp | 4 ++-- SparcRegisterInfo.cpp | 9 ++++----- 2 files changed, 6 insertions(+), 7 deletions(-) Index: llvm/lib/Target/Sparc/FPMover.cpp diff -u llvm/lib/Target/Sparc/FPMover.cpp:1.12 llvm/lib/Target/Sparc/FPMover.cpp:1.13 --- llvm/lib/Target/Sparc/FPMover.cpp:1.12 Sat Feb 4 23:50:24 2006 +++ llvm/lib/Target/Sparc/FPMover.cpp Thu May 4 12:52:23 2006 @@ -104,8 +104,8 @@ else assert(0 && "Unknown opcode!"); - MI->SetMachineOperandReg(0, EvenDestReg); - MI->SetMachineOperandReg(1, EvenSrcReg); + MI->getOperand(0).setReg(EvenDestReg); + MI->getOperand(1).setReg(EvenSrcReg); DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI); // Insert copy for the other half of the double. if (DestDReg != SrcDReg) { Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.42 llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.43 --- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.42 Thu May 4 12:21:19 2006 +++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp Thu May 4 12:52:23 2006 @@ -135,8 +135,8 @@ if (Offset >= -4096 && Offset <= 4095) { // If the offset is small enough to fit in the immediate field, directly // encode it. - MI.SetMachineOperandReg(i, SP::I6); - MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate, Offset); + MI.getOperand(i).ChangeToRegister(SP::I6); + MI.getOperand(i+1).ChangeToImmediate(Offset); } else { // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to // scavenge a register here instead of reserving G1 all of the time. @@ -146,9 +146,8 @@ BuildMI(*MI.getParent(), II, SP::ADDrr, 2, SP::G1).addReg(SP::G1).addReg(SP::I6); // Insert: G1+%lo(offset) into the user. - MI.SetMachineOperandReg(i, SP::G1); - MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate, - Offset & ((1 << 10)-1)); + MI.getOperand(i).ChangeToRegister(SP::G1); + MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1)); } } _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits