Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.27 -> 1.28
SelectionDAGISel.h updated: 1.20 -> 1.21
---
Log message:
Introducing plugable register allocators and instruction schedulers.
---
Diffs of the changes: (+16 -14)
ScheduleDAG.h | 26 ++++++++++++++++----------
SelectionDAGISel.h | 4 ----
2 files changed, 16 insertions(+), 14 deletions(-)
Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.27
llvm/include/llvm/CodeGen/ScheduleDAG.h:1.28
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.27 Wed May 24 12:04:03 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h Tue Aug 1 09:21:23 2006
@@ -221,29 +221,35 @@
std::map<SDNode*, unsigned> &VRBaseMap);
};
- ScheduleDAG *createBFS_DAGScheduler(SelectionDAG &DAG, MachineBasicBlock
*BB);
+ /// createBFS_DAGScheduler - This creates a simple breadth first instruction
+ /// scheduler.
+ ScheduleDAG *createBFS_DAGScheduler(SelectionDAG *DAG, MachineBasicBlock
*BB);
/// createSimpleDAGScheduler - This creates a simple two pass instruction
- /// scheduler.
- ScheduleDAG* createSimpleDAGScheduler(bool NoItins, SelectionDAG &DAG,
+ /// scheduler using instruction itinerary.
+ ScheduleDAG* createSimpleDAGScheduler(SelectionDAG *DAG,
MachineBasicBlock *BB);
+ /// createNoItinsDAGScheduler - This creates a simple two pass instruction
+ /// scheduler without using instruction itinerary.
+ ScheduleDAG* createNoItinsDAGScheduler(SelectionDAG *DAG,
+ MachineBasicBlock *BB);
+
/// createBURRListDAGScheduler - This creates a bottom up register usage
/// reduction list scheduler.
- ScheduleDAG* createBURRListDAGScheduler(SelectionDAG &DAG,
+ ScheduleDAG* createBURRListDAGScheduler(SelectionDAG *DAG,
MachineBasicBlock *BB);
/// createTDRRListDAGScheduler - This creates a top down register usage
/// reduction list scheduler.
- ScheduleDAG* createTDRRListDAGScheduler(SelectionDAG &DAG,
+ ScheduleDAG* createTDRRListDAGScheduler(SelectionDAG *DAG,
MachineBasicBlock *BB);
/// createTDListDAGScheduler - This creates a top-down list scheduler with
- /// the specified hazard recognizer. This takes ownership of the hazard
- /// recognizer and deletes it when done.
- ScheduleDAG* createTDListDAGScheduler(SelectionDAG &DAG,
- MachineBasicBlock *BB,
- HazardRecognizer *HR);
+ /// a hazard recognizer.
+ ScheduleDAG* createTDListDAGScheduler(SelectionDAG *DAG,
+ MachineBasicBlock *BB);
+
}
#endif
Index: llvm/include/llvm/CodeGen/SelectionDAGISel.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.20
llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.21
--- llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.20 Thu Jul 27 20:03:48 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGISel.h Tue Aug 1 09:21:23 2006
@@ -67,10 +67,6 @@
/// folded during instruction selection?
virtual bool CanBeFoldedBy(SDNode *N, SDNode *U) { return true; }
- /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
- /// to use for this target when scheduling the DAG.
- virtual HazardRecognizer *CreateTargetHazardRecognizer();
-
/// CaseBlock - This structure is used to communicate between SDLowering and
/// SDISel for the code generation of additional basic blocks needed by
multi-
/// case switch statements.
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