Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.404 -> 1.405 --- Log message: Fix a bug legalizing zero-extending i64 loads into 32-bit loads. The bottom part was always forced to be sextload, even when we needed an zextload. --- Diffs of the changes: (+2 -3) LegalizeDAG.cpp | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.404 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.405 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.404 Fri Oct 6 12:34:12 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Oct 6 19:58:36 2006 @@ -4474,13 +4474,12 @@ SDOperand Chain = Node->getOperand(0); SDOperand Ptr = Node->getOperand(1); MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); - unsigned LType = Node->getConstantOperandVal(4); + ISD::LoadExtType LType = (ISD::LoadExtType)Node->getConstantOperandVal(4); if (EVT == NVT) Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); else - Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), - EVT); + Lo = DAG.getExtLoad(LType, NVT, Chain, Ptr, Node->getOperand(2), EVT); // Remember that we legalized the chain. AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits