Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.287 -> 1.288
X86ISelLowering.h updated: 1.78 -> 1.79
X86InstrSSE.td updated: 1.169 -> 1.170
---
Log message:
Fixed a bug which causes x86 be to incorrectly match
shuffle v, undef, <2, ?, 3, ?>
to movhlps
It should match to unpckhps instead.
Added proper matching code for
shuffle v, undef, <2, 3, 2, 3>
---
Diffs of the changes: (+30 -5)
X86ISelLowering.cpp | 18 +++++++++++++++++-
X86ISelLowering.h | 5 +++++
X86InstrSSE.td | 12 ++++++++----
3 files changed, 30 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.287
llvm/lib/Target/X86/X86ISelLowering.cpp:1.288
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.287 Thu Nov 2 14:25:49 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Nov 7 16:14:24 2006
@@ -2582,6 +2582,22 @@
isUndefOrEqual(N->getOperand(3), 3);
}
+/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
+/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
+/// <2, 3, 2, 3>
+bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
+ assert(N->getOpcode() == ISD::BUILD_VECTOR);
+
+ if (N->getNumOperands() != 4)
+ return false;
+
+ // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
+ return isUndefOrEqual(N->getOperand(0), 2) &&
+ isUndefOrEqual(N->getOperand(1), 3) &&
+ isUndefOrEqual(N->getOperand(2), 2) &&
+ isUndefOrEqual(N->getOperand(3), 3);
+}
+
/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
bool X86::isMOVLPMask(SDNode *N) {
@@ -3724,7 +3740,7 @@
SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
&IdxVec[0], IdxVec.size());
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
- Vec, Vec, Mask);
+ Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
DAG.getConstant(0, getPointerTy()));
} else if (MVT::getSizeInBits(VT) == 64) {
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.78
llvm/lib/Target/X86/X86ISelLowering.h:1.79
--- llvm/lib/Target/X86/X86ISelLowering.h:1.78 Tue Oct 31 14:13:11 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Tue Nov 7 16:14:24 2006
@@ -186,6 +186,11 @@
/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
bool isMOVHLPSMask(SDNode *N);
+ /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical
form
+ /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
+ /// <2, 3, 2, 3>
+ bool isMOVHLPS_v_undef_Mask(SDNode *N);
+
/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a shuffle of elements that is suitable for input to
MOVLP{S|D}.
bool isMOVLPMask(SDNode *N);
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.169
llvm/lib/Target/X86/X86InstrSSE.td:1.170
--- llvm/lib/Target/X86/X86InstrSSE.td:1.169 Fri Nov 3 17:48:56 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Nov 7 16:14:24 2006
@@ -110,6 +110,10 @@
return X86::isMOVHLPSMask(N);
}]>;
+def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
+ return X86::isMOVHLPS_v_undef_Mask(N);
+}]>;
+
def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
return X86::isMOVHPMask(N);
}]>;
@@ -1987,16 +1991,16 @@
MOVHLPS_shuffle_mask)),
(MOVHLPSrr VR128:$src1, VR128:$src2)>;
-// vector_shuffle v1, undef <2, 3, ?, ?> using MOVHLPS
+// vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
- UNPCKH_shuffle_mask)),
+ MOVHLPS_v_undef_shuffle_mask)),
(MOVHLPSrr VR128:$src1, VR128:$src1)>;
def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
- UNPCKH_shuffle_mask)),
+ MOVHLPS_v_undef_shuffle_mask)),
(MOVHLPSrr VR128:$src1, VR128:$src1)>;
}
- let AddedComplexity = 20 in {
+let AddedComplexity = 20 in {
// vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
// vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
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