Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.303 -> 1.304 X86InstrSSE.td updated: 1.172 -> 1.173 --- Log message: If we have ScalarSSE, we can select bitconvert into single instructions. This compiles bitcast.ll:test3/test4 into: _test3: movd %xmm0, %eax ret _test4: movd %edi, %xmm0 ret --- Diffs of the changes: (+14 -2) X86ISelLowering.cpp | 6 ++++-- X86InstrSSE.td | 10 ++++++++++ 2 files changed, 14 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.303 llvm/lib/Target/X86/X86ISelLowering.cpp:1.304 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.303 Tue Dec 5 12:22:22 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Dec 5 12:45:06 2006 @@ -145,8 +145,10 @@ } // TODO: when we have SSE, these could be more efficient, by using movd/movq. - setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); - setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); + if (!X86ScalarSSE) { + setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); + setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); + } if (Subtarget->is64Bit()) { setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand); setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand); Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.172 llvm/lib/Target/X86/X86InstrSSE.td:1.173 --- llvm/lib/Target/X86/X86InstrSSE.td:1.172 Thu Nov 16 17:33:25 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue Dec 5 12:45:06 2006 @@ -1683,6 +1683,11 @@ [(set VR128:$dst, (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>; +def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (ops FR32:$dst, GR32:$src), + "movd {$src, $dst|$dst, $src}", + [(set FR32:$dst, (bitconvert GR32:$src))]>; + + // SSE2 instructions with XS prefix def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src), "movq {$src, $dst|$dst, $src}", @@ -1724,6 +1729,11 @@ [(store (i32 (vector_extract (v4i32 VR128:$src), (iPTR 0))), addr:$dst)]>; +def MOVDSS2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, FR32:$src), + "movd {$src, $dst|$dst, $src}", + [(set GR32:$dst, (bitconvert FR32:$src))]>; + + // Move to lower bits of a VR128, leaving upper bits alone. // Three operand (but two address) aliases. let isTwoAddress = 1 in { _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits